The main objective of this article is to design an AND gate using Verilog. But before starting to code, we need proper knowledge of basic logic gates in Verilog. The two basic logic gates are AND and OR gates in which the name suggested. The following figure shows a basic NAND gate, Gate Level Modeling, Data Flow Modeling, Behavioural Modeling, RTL Simulation and Truth Table of NAND.

course |
Verilog Tutorial |

Category |
VLSI Design |

Verilog Programming For |
NOT Gate |

Examples |
Verilog |

An AND gate is a logic gate with two or more inputs and a single output. An AND gate works according to logical multiplication rules. In this gate, if either input is low (0), then the output is also low. If all inputs are high (1), then the output is also high. An AND gate can have any number of inputs, although 2-input and 3-input AND gates are the most common.

There are many integrated circuits that use this logic, which we will come back to later. First, let's better understand how the output of an AND gate behaves in relation to its inputs.

There are two binary digits - 0 and 1. We just said that an AND gate performs binary multiplication of binary digits. If we multiply 0 by 0 we get 0, 1 by 0 or 0 by 1 we get 0. We only get 1 when 1 is multiplied by 1.

## AND Gate

AND Gate symbol

Y = A.B or say Y = A & B.

The AND Gate have 2 input and a single output where A, and B are the inputs and Y is the output. In And Gate, the output will be high only if both inputs are high (1) otherwise it will be low (0)

Input A | Input B | Output y |

0 | 0 | 0 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 1 |

Truth Table

## Gate Level Modeling

We can design a logical circuit using basic logical gates with Gate level modeling. Verilog supports encoding circuits using sensible gateways as pre-defined elements. These primitives are validated as modules unless they are pre-defined in Verilog and do not require module definitions.

A gate and a basic gate where the output is equal to the output of the inserted material. The output of this gate is only high if both inputs are high otherwise the result is low. Here is a logical representation of the gate AND.

The AND gate is a basic logic gate that performs the logical function, binary AND. When both the inputs are at logic 1, then their corresponding outputs will also to logic ‘1’. Either input at 0 will result in the corresponding output being at 0. This is because AND gate follows the law of A ⊕ B=A+B where A represents the first input signal and B represents the second input signal.

module And_Gate_Gate_Level(a,b,y);input a,b;output y;and (y,a,b);endmodule

## Data Flow Modeling

Compared to gate-level modeling, data flow modeling in Verilog has a higher level of inaccessibility. What this means, you do not really need to know the design of the circuit. That really helps because modeling at the gate level becomes very difficult in a complex cycle.

Data flow modeling is therefore a very important way to use design. You need to know the boolean logic equation of the circuit breaker according to its input. We use continuous assignments to simulate data flow across multiple designs. Continuous assignments are done using the keyword assign. You will see how it works slowly.

Data Flow modelling is the same as Gate Level Modeling the difference is that instead of using directly in data flow we use operations. Here we use a single operator & (for multiply). Here firstly we multiply both inputs and the result will be only 1 if both inputs are 1

**For example:**if two input is 0 and 1, if we multiply both inputs we get output as 0. So Output will be only 1 if we have both

module And_Gate_Data_Flow(a,b,y);input a,b;output y;assign y = a&b;endmodule

## Test Bench

The code shown below is the test bench for AND Gate. It is used to give values for Input of AND Gate. Here a=0; b=0; represent the values of input at A and B. #100 represents the wait time. So that we can get a clear waveform in RTL simulation. The output of AND Gate will be opposite to the NAND Gate.

module And_Gate_test;// Inputsreg a;reg b;// Outputswire y;// Instantiate the Unit Under Test (UUT)And_Gate uut (.a(a),.b(b),.y(y));initial begin// Initialize Inputsa=0;b=0;#100 a=0;b=1;#100 a=1;b=0;#100 a=1;b=1;#100;// Add stimulus hereendendmodule

## RTL Simulation

Here we represent Register Transfer Level (RTL) For AND Gate for both Data Level and Data Flow modelling. Both Data level and Data Flow AND Gate show the same waveform

By checking the above waveform we can determine whether our waveform is right or wrong by comparing it with the truth table given above. This waveform has to match with the same truth table of AND Gate.

**Read Also**