Verilog Program for XNOR gate | VLSI Modeling

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Verilog Program for XNOR  gate | VLSI Modeling

The “XNOR” gate is Nand’s double-entry gate. It has only one output called not output. The conduct of this region can be understood in its own name. If exactly one of the gate inputs is high, then the input will be high. If both inputs are low, that means the input will be high. If there is no high input, the high-value signal in all inputs will make the output low.

Xnor Gate

Verilog code for XNOR Gate


XNOR Gate symbol


The XNOR Gate have 2 input and a single output where A and B are the inputs and Y is the output. In Xxnor Gate, the output will be High only if both inputs are low (0) or both inputs are high
The Boolean equation of an XNOR gate is Y = AB + A’B’.

Input A
Input B
Output y
0
0
1
0
1
0
1
0
0
1
1
1

Truth Table

Gate Level Modeling

Designing circuits using basic logic gates is known as a gate-level model. Since gates are an integral part of any logic design, gate primitives can be used to create complex level concepts such as multiplexers, and encoders. Gate level analysis also takes care of gate delays, which is not possible at a high output level.

Xnor Gate is a Universal Gate. XNOR Gate has two inputs AB and a single output Y. When both inputs are 0 0 output is 1 when one input is 0 and another input is 1 then the output is 0 when one input is 1 and another input is 0 then the output is 0 and when both inputs are 1 the output will be 1


module Xnor_Gate(a,b,y);
input a,b;
output y;
xnor (y,a,b);
endmodule

Data Flow Modeling

compared to modeling at the gate level, data flow modeling makes the meaning more visible.

Dataflow modeling defines circuits for their function rather than their gate structure. The module is used to determine how data flows between registers. It is a much simpler method than measuring the level of the gate, which is often as difficult as the weight of the circuit.

Therefore, data flow modeling is a very important way to use design. This design style requires continuous assignment statements. Ongoing activities are done using the keyword assigned. Here is a list of all the keywords in Verilog if you would like to brush your memory.

Instead of using directly in data flow we use operations such as & (Bit-Wise AND), * (Multiply), % (Modulus), + (Plus), - (Minus) && (Logical AND) etc in Data Flow modelling . Verilog provides 30 different types of Operators. It is used to describe combinational circuits.

module Xnor_Gate_Data_Flow(a,b,y);
input a,b;
output y;
assign y = ~(a^b);
endmodule

Test Bench

The code shown below is the test bench for Xnor Gate. It is used to give values for Input of Xxnor Gate. Here a=0; b=0; represent the values of input at A and B. #100 represents the wait time. So that we can get a clear waveform in RTL simulation

module Xnor_Gate;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire y;

    // Instantiate the Unit Under Test (UUT)
    Xnor_Gate_Flow uut (
        .a(a),
        .b(b),
        .y(y)
    );

    initial begin
        // Initialize Inputs
        a = 0;b = 0;
      #100 a=0;b=1;
      #100 a=1;b=0;
      #100 a=1;b=1;

        // Wait 100 ns for global reset to finish
        #100;
       
        // Add stimulus here

    end
     
endmodule

RTL Simulation

Here we represent Register Transfer Level (RTL) For XNOR Gate for both Data Level and Data Flow modelling. 

Verilog RTL Simulation Of XNOR Gate



By looking at the waveforms, we can find that whenever both inputs A and B are the same, then the output is higher, if not in all other cases, the output is lower. By checking the above waveform we can determine whether our waveform is right or wrong by comparing it with the truth table given above. This waveform has to match with the same truth table of XNOR Gate.

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