Verilog Program for Half Adder | VLSI Modeling

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Verilog Program for Half Adder | VLSI Modeling

Half adders are the basic building block of new digital designers. The half-adder shows how two pieces can be added and a few simple logic gates. In practice, they are rarely used because they are limited to one input. To add large numbers Full-Adder can be used. The half-adder has two inputs, one output, and an output. See the fact table below to see how these pieces work. The code creates a half adder. There is also a test bench that encourages design and ensures proper behaviour.

Half Adder Logic Circuit 

Verilog code for Half Adder

Half Adder logical Diagram 

A half adder is a combination arithmetic circuit that takes two binary digits and adds them. The half adder offers two outputs, SUM performance and CARRY manufactured in operation. Since this load can be added to the final response, the add-on process is incomplete in some way. Therefore, it is known as a half adder
SUM =  A XOR B  |  CARRY = A.B

A
B
Sum
Carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1

Truth Table

Gate Level Modeling


The half adder circuit adds two separate bits and ignores any load when made. Since any addition to the load is incomplete without adding a load, the function is incomplete. The cycle is therefore known as the half-adder. Let's write a fact table using normal Boolean logic to compile
0 + 0 = Sum - 0 | Carry - 0
0 + 1 = Sum - 1 | Carry - 0
1 + 0 = Sum - 1 | Carry - 0
1 + 1 = Sum - 0 | Carry - 1

module Half_Adder(a,b,s,c);
input a,b;
output s,c;
xor (s,a,b);
and (c,a,b);
endmodule

Data Flow Modeling

Dataflow modeling uses functions that define the functionality of a circuit instead of its gate structure. The designer should keep in mind how data flows within the design. Data flow modeling has become a popular design method, as the tools for logical integration become more sophisticated. This approach allows the designer to focus on expanding the region in line with the flow of data.

module Half_Adder_Data_Flow(a,b,s,c);
input  a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

Test Bench

Testbench drives the input into the system design code. It is used to give initial incentives to input signals and to evaluate a whole range of possible combinations. You can find a detailed explanation and steps for writing a testbench here!

This is a Half Adder testbench code.

module Half_Adder;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire s;
    wire c;

    // Instantiate the Unit Under Test (UUT)
    Half_Adder_Flow uut (
        .a(a),
        .b(b),
        .s(s),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;b = 0;
      #100 a=0;b=1;
      #100 a=1;b=0;
      #100 a=1;b=1;

        // Wait 100 ns for global reset to finish
        #100;
       
        // Add stimulus here

    end
     
endmodule

RTL Simulation

Here we represent Register Transfer Level (RTL) For Half Adder Mux for both Data Level and Data Flow modelling. 

Verilog RTL Simulation Of Half Adder


Here is the final modified waveform of the Half Adder circuit.

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