Verilog Program for 2:1 Mux | VLSI Modeling

Verilog Program for 2:1 Mux | VLSI Modeling

A multiplexer is a device that selects one output for multiple inputs. Also known as a data selector. Multiplexers are used in communication systems to increase the amount of data that can be sent over a network over a certain period of time and bandwidth. It allows us to 'compress' multiple data lines into a single data line. In this post, we will discuss the modelling of the 2:1 Mux from top-down and bottom-up. The following figure shows a basic 2:1 Mux logic circuit, Gate Level Modeling, Data Flow Modeling, Behavioural Modeling, RTL Simulation and Truth Table of 2:1 Mux.

2:1 Mux Logic Circuit 

Verilog code for 2:1 MUX

2:1 Mux logical Diagram 

To compare 2: 1 with 2 ^ n: 1 (as mentioned earlier) we get n = 1, which is the number of selected lines (variable input = 2, select lines = 1, exit signal = 1).

The input signals are D0 and D1. S is the selected line with Y as its output. We can verbally verify the output of the output that:
The equation for 2:1 mux is: Y = D0.S ’+ D1.S

Select Lines (S)
Input D0
Input D1
Output Y

Truth Table

Gate Level Modeling

At the gate level, we will first announce the 2: 1 MUX module, followed by the output-input signal. The flexibility of the input and output input is important here, the output variable is written first in brackets, and then input.
The module is the keyword here. m21 name of the module. Y is the output and D0, D1 and S are the inputs written after that. Note that we do not broadcast central signals when defining a module.

Next comes the announcement of the input, output, and intermediate signals. You may have noticed that some modeling styles include the declaration of variables and their data types. But at the gate level, we only announce the intermediate variables like the fence; there is no need for reg or commercial announcement of the output input-output.
Next comes the partial instantiation of the gates. and not even though the predefined gates are built inside, and we secure these gates with separate exit holes.

For example, not a gateway, Sbar is the result and S is the installation. Similarly gate and T1, D1, and T2, D2 are both inputs and gates and S and Sbar output respectively.

The end module marks the end of the module. Here is the final 2: 1 mux code using the gate-level model.

module Two_Is_To_One_Mux(d0,d1,s,y);
input d0,d1,s;
output y;
assign y=s ? d1 : d0;

Data Flow Modeling

To start with this, first of all, you need to announce the module. There is no need to announce the type of data in this model.

Now that this is a style of data flow, one has to use sharing statements. I used a ternary operator to output Y. This operator? means that the output Y is equal to the data D1 if selecting line S is true otherwise D0 is the end result.

module Two_Is_To_One_Mux_Data_Flow(d0,d1,s0,y);
input d0,d1,s0;
output y;
wire a1,a2,a3;
assign a1 = ~ s0;
assign a2 = a1 & d0;
assign a3= d1 & s0;
assign y = a2|a3;

Test Bench

Testbench drives the input into the system design code. It is used to give initial incentives to input signals and to evaluate a whole range of possible combinations. You can find a detailed explanation and steps for writing a testbench here!

This is a 2: 1 multiplexer testbench code.

module Two_Is_To_One_Mux;

    // Inputs
    reg d0;
    reg d1;
    reg s0;

    // Outputs
    wire y;

    // Instantiate the Unit Under Test (UUT)
    Mux_Flow uut (

    initial begin
        // Initialize Inputs
        s0 = 0;d0 = 0;d1 = 0;
        #100;s0 = 0;d0 = 0;d1 = 1;
        #100;s0 = 1;d0 = 1;d1 = 0;
        #100;s0 = 1;d0 = 1;d1 = 1;

        // Wait 100 ns for global reset to finish
        // Add stimulus here


RTL Simulation

Here we represent Register Transfer Level (RTL) For 2:1 Mux for both Data Level and Data Flow modelling. 

Verilog RTL Simulation Of 2:1 Mux

Here is the final modified waveform of the 2X1 MUX circuit.

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