# Verilog Program for OR gate | VLSI Modeling

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We all know that gateway is a digital logic circuit, when combined, we can perform simple logical operations on data. In this post, we will discuss the model of the OR gate from top to bottom and bottom to top. The following figure shows the basic OR gateway, Gate Level Modeling, Data Flow Modeling, Behavioral Modeling, RTL Simulation and OR Truth Table

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An OR gate is a logic gate that performs a logical OR operation. A logical OR operation has a high (1) output when one or both of the gate's inputs are high (1). If neither input is high, the output is low (0). Just like an AND gate, an OR gate can have any number of input probes, but only one output probe. The function of a logical OR gate effectively finds the maximum between two binary digits, just as the complementary AND function finds the minimum. The logical symbol of the 2-input OR gate is shown below:

## OR Gate

OR Gate symbol

The OR Gate have 2 input and a single output where A, B are the inputs and Y is the output. In OR Gate, the output will be low only if both inputs are low (0)

The boolean equation of an OR gate is  Y = A + B.

 Input A Input B Output y 0 0 0 0 1 1 1 0 1 1 1 1

Truth Table

## Gate Level Modeling

Designing a complex circuit using basic logic gates is the goal of modeling at the gate level. We specify regional gates in our code. Verilog supports defining circuits using logical gates as pre-defined elements. These primitives are validated as modules unless they are pre-defined in Verilog and do not require module definitions.

OR Gate is a Universal Gate. OR Gate has two inputs AB and a single output Y. When both inputs are 0 0 output is 0 when one input is 0 and another input is 1 then output is 1, when one input is 1 and another input is 0 then output is 1 and when both inputs are 1 the output will be 1

`module Or_Gate(a,b,y);input a,b;output y;or (y,a,b);endmodule`

## Data Flow Modeling

Compared to gate-level modeling, data flow modeling is a high level of inaccessibility. Dataflow modeling defines circuits for their function rather than their gate structure. That is helpful because modeling at the gate level is very difficult for large circuits because let's face it, the digital cycle with a lot of gates can seem very difficult.

Therefore, data flow modeling is a very important way to use design. We need a boolean logic equation and ongoing allocation statements to build projects. Continuous assignments are done using the keyword assign.

Instead of using directly in data flow we use operations such as & (Bit-Wise AND), * (Multiply), % (Modulus), + (Plus), - (Minus) && (Logical AND) etc in Data Flow modelling . Verilog provides 30 different types of Operators. It is used to describe combinational circuits.

`module Or_Gate_Data_Flow(a,b,y);input a,b;output y;assign y=a|b;endmodule`

## Test Bench

The code shown below is the test bench for OR Gate. It is used to give values for Input of OR Gate. Here a=0; b=0; represent the values of input at A and B. #100 represents the wait time. So that we can get a clear waveform in RTL simulation

`module Or_Gate;    // Inputs    reg a;    reg b;    // Outputs    wire y;    // Instantiate the Unit Under Test (UUT)    os_lab_flow uut (        .a(a),         .b(b),         .y(y)    );    initial begin        // Initialize Inputs              a = 0;b = 0;            #100;   a = 0;b = 1;            #100;   a = 1;b = 0;                #100;   a = 1;b = 1;                        // Wait 100 ns for global reset to finish        #100;                // Add stimulus here    end      endmodule`

## RTL Simulation

Here we represent Register Transfer Level (RTL) For OR Gate for both Data Level and Data Flow modelling.

By checking the above waveform we can determine whether our waveform is right or wrong by comparing it with the truth table given above. This waveform has to match with the same truth table of OR Gate.

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