Verilog Program For NOT Gate | VLSI Modeling

Verilog Program for NOT gate | VLSI Modeling

The “not” gate is Nand’s double-entry gate. It has only one output called not output. The conduct of this region can be understood in its own name. If one of the gate inputs is high, the input will be high. If both inputs are low, that means the input will be high. If there is no high input, the high-value signal in all inputs will make the output low.

course Verilog Tutorial
Category VLSI Design
Verilog Programming For NOT Gate
Examples Verilog

A NOT gate is a logic gate that inverts the digital input signal. For this reason, a NOT gate is sometimes called an inverter (not to be confused with a power inverter). A NOT gate always has a high (logic 1) output if its input is low (logic 0). Conversely, a logical NOT gate will always have a low (logical 0) output if the input is high (logical 1).The logical symbol for a NOT gate is shown below:

NOT Gate

Verilog code for NOT Gate

OR Gate symbol


The NOT Gate have 1 input and a single output where A is the input and Y is the output. In NOT Gate, the output will be High only if both inputs are low (0) and vice versa

Input(A) Output(Y)
0 1
1 0

Truth Table

Gate Level Modeling

Computer hardware design at this level is accurate for the user with a basic knowledge of digital imagination design because it is possible to see one-to-one connections between a logical circuit diagram and a Verilog description. The logic circuit can be designed using sensible gates. Verilog supports basic logic gates as pre-defined primitives. These primitives are validated as modules unless they are pre-defined in Verilog and do not require module definitions. All logical circuits can be designed using basic gates.

NOT Gate is a Universal Gate. NOT Gate has one inputs A and a single output Y. When both inputs are 0 output is 1 and the input is 1 the output is zero
The boolean equation of a NOT gate is Y = A’.


module Not_Gate(a,y);
input a;
output y;
not (y,a);
endmodule

Data Flow Modeling

For smaller circuits, the gate level matching method works because the number of gates is limited, and the designer can verify and interact with each gate. Also, modelling at the gate level is accurate for the designer.

However, the designer cannot design when the number of gates is large. So we have a data flow model, where we use the function at a take-up level higher than the gate level.

Verilog allows us to design the region based on the flow of data between registers and the way data is processed instead of taking gate action. The data flow method allows us to focus on increasing the region by the data flow.

Instead of using directly in data flow we use operations such as & (Bit-Wise AND), * (Multiply), % (Modulus), + (Plus), - (Minus) && (Logical AND) etc in Data Flow modelling . Verilog provides 30 different types of Operators. It is used to describe combinational circuits.


module Not_Gate_Data_Flow(a,y);
input a;
output y;
assign y = ~a;
endmodule

Test Bench

The code shown below is the test bench for NOT Gate. It is used to give values for Input of NOT Gate. Here a=0;  represent the values of input at A  #100 represents the wait time. So that we can get a clear waveform in RTL simulation

module Not_Gate;

    // Inputs
    reg a;

    // Outputs
    wire y;

    // Instantiate the Unit Under Test (UUT)
    Not_Gate_Flow uut (
        .a(a),
        .y(y)
    );

    initial begin
        // Initialize Inputs
             a = 0;
        #100;a = 1;

        // Wait 100 ns for global reset to finish
        #100;
       
        // Add stimulus here

    end
     
endmodule

RTL Simulation

Here we represent Register Transfer Level (RTL) For NOT Gate for both Data Level and Data Flow modelling. 

Verilog RTL Simulation Of NOT Gate



By looking at the waveforms, we can find that whenever the input A is low, then the output is high, if not the output is low.
By checking the above waveform we can determine whether our waveform is right or wrong by comparing it with the truth table given above. This waveform has to match with the same truth table of NOT Gate.

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